The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. A typical planar MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes.
In contrast to traditional planar (MOSFETs), which are fabricated using conventional lithographic fabrication methods, non-planar MOSFETs incorporate various vertical transistor structures, and typically include two or more gate structures formed in parallel. One such semiconductor device is the “FinFET,” which takes its name from the multiple thin silicon “fins” that are used to form the respective gate channels, and which are typically on the order of tens of nanometers in width.
As the size of the electrical devices that form the IC are made smaller and smaller, ever greater demands are placed on the techniques used to form these features, particularly the fins of a FinFET device. For example, photolithography is commonly used to pattern device features, such as conductive lines, on a substrate. “Pitch” is the center-to-center distance between features of an integrated circuit such as fins. Due to optical factors such as light or radiation wavelength, however, photolithography techniques have a minimum pitch below which features cannot be formed reliably. Thus, the minimum pitch of a photolithographic technique can limit feature size reduction.
One technique commonly used for extending the capabilities of photolithographic techniques beyond their minimum pitch to form more closely spaced fins is the “pitch doubling” technique. In this technique, photolithography is first used to form a pattern of lines in a photoresist layer overlying a layer of a temporary or expendable material and a substrate. Common wavelengths that are used in performing the photolithography include, but are not limited to, 157 nm, 193 nm, 248 nm or 365 nm. Before performing subsequent processing steps, the lines are optionally shrunk using an isotropic etch. The pattern is then transferred by an etch step, such as an anisotropic etch step, to the layer of expendable material, thereby forming placeholders or mandrels. The photoresist lines can be stripped and the mandrels can be isotropically etched to increase the distance between neighboring mandrels. A layer of spacer material is subsequently deposited over the mandrels. Spacers are then formed on the sides of the mandrels by preferentially etching the spacer material from the horizontal surfaces in a directional spacer etch. The remaining mandrels are then removed, leaving behind only the spacers, which together act as a mask for patterning. Thus, where a given pattern area formerly defined one feature and one space (each having a width F, for a pitch of 2F), the same pattern area now includes two features and two spaces, as defined by the spacers (each having a width ½F, for a pitch of F). Consequently, the smallest feature size possible with a photolithographic technique is effectively decreased by using the pitch doubling technique.
While pitch of the fins is actually reduced using these techniques, this reduction in pitch is conventionally referred to as “pitch doubling”, or more generally, “pitch multiplication”. This is because these techniques allow the number of features in a given region of the substrate to be doubled, or more generally, multiplied. Thus, using the conventional terminology, “multiplication” of pitch by a certain factor actually involves reducing the pitch by that factor. By forming multiple layers of spacers upon each other, the definable feature size can be made even smaller. Thus, the terms “pitch multiplication” and “pitch doubling” refer to the process generally, regardless of the number of times the spacer formation process is employed.
Pitch multiplication techniques, however, are cost and time prohibitive for many fabrication applications. Pitch multiplication techniques are also very sensitive to process variations, which may result in a high device failure rate. Thus, alternatives to pitch multiplication techniques are constantly being sought for fabricating FinFET ICs with sub-lithographic features.
One alternative technique that has previously been employed in small-scale fabrication applications (for example, single wafer research and testing) is laser interference lithography (LIL), also known as interferometric lithography. In interferometric lithographic systems, a laser beam is sent into a beam splitter, the beam splitter divides the laser beam, and then the laser beam is recombined at a substrate that is being exposed, to form a pattern. Typically the patterns being formed involve lines, or rulings (also referred to as “stripes”), which are used to test such components as photoresist, etc. Thus, in an interferometric lithographic system, two laser beams are coherently matched, to form fringes at the substrate plane. The fringe pattern exposes the photoresist, which forms a type of a grating pattern. Different interferometric lithographic systems have different ways of generating the two laser beams that will ultimately produce the interference fringes at the substrate.
In conventional interferometric lithographic systems, in order to change the resolution of the system, it is generally necessary to change a number of parameters of the optical system. Typically, this involves replacing some elements of the optics modules. This procedure can be time consuming. Additionally, replacing optical elements or components frequently requires realignment of the components, further increasing the time that the procedure requires. For example, one of the parameters that needs to change in order to change the resolution of the system is the angle at which the laser beams strike the substrate. This may be viewed as analogous to changing the numerical aperture of the optical system (although, since lenses are not involved in formation of the image in interferometric systems, the numerical aperture at issue is more of a derivative concept).
Other parameters that may need to be changed involve how the beams are separated, and the alignment of various optical components needed to produce the interference fringes. Because of the relatively small coherence length of the laser, there is generally little room for the optical designer to work with, in making sure that the two laser beams actually form the required fringes. In other words, the alignments have to be exact, which is often very difficult to achieve in practical systems, particularly where optical components have to be swapped in and out of the system. Having changeable optical elements drives the system complexity and cost upward. Each time a user has to change a beam splitter or an optical module, there is risk of losing critical alignments. Further, LIL methods can only produce a regular stripe pattern, not any of the complex shapes and patterns, such as fin patterns in a FinFET IC, typically required in commercially viable IC designs. Thus, as noted above, LIL has been largely limited to experimental and research applications.
Accordingly, it is desirable to provide improved methods for fabricating FinFET integrated circuits including sub-lithographic features. Additionally, it is desirable to provide methods for patterning a substrate using laser interference lithography that is useful to form complex and irregular fin patterns. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.